Today's semiconductor technology is rapidly forcing device sizes below the 0.5 micron level, even to the 0.25 micron size. With device sizes on this order, ever higher precision is being demanded of the processes that form and shape the devices and the dielectric layers separating the active devices. In the fabrication of semiconductor components, the various devices are formed in layers upon an underlying substrate typically composed of silicon, germanium, or gallium arsenide. Metal conductor lines form interconnects between the various discrete devices. The metal conductor lines are further insulated from the next interconnection level by thin films of insulating material deposited by, for example, CVD (Chemical Vapor Deposition) of oxide or application of SOG (Spin On Glass) layers followed by fellow processes. Holes, or vias, formed through the insulating layers provide electrical connectivity between successive conductive interconnection layers. In such microcircuit wiring processes, it is highly desirable that the insulating layers have a smooth surface topography, since it is difficult to lithographically image and pattern layers applied to rough surfaces.
One semiconductor manufacturing process, chemical mechanical polishing (CMP), is used to provide the necessary smooth semiconductor topographies. CMP can be used for planarizing: (a) insulator surfaces, such as silicon oxide or silicon nitride, deposited by chemical vapor deposition; (b) insulating layers, such as glasses deposited by spin-on and reflow deposition means, over semiconductor devices; or (c) metallic conductor interconnection wiring layers. Semiconductor wafers may also be planarized to: control layer thickness, sharpen the edge of via "plugs," remove a hardmask, remove other material layers, etc. Significantly, a given semiconductor wafer may be planarized several times, such as upon completion of each metal layer. For example, following via formation in a dielectric material layer, a metallization layer is blanket deposited and then CMP is used to produce planar metal studs.
Briefly, the CMP process involves holding and rotating a thin, reasonably flat, semiconductor wafer against a rotating polishing surface. A chemical slurry, under controlled chemical, pressure, and temperature conditions wets the polishing surface. The chemical slurry contains a polishing agent, such as alumina or silica, which is used as the abrasive material. Additionally, the slurry contains selected chemicals to etch or oxidize selected surfaces of the wafer to prepare them for removal by the abrasive. The combination of both a chemical reaction and mechanical removal of the material during polishing results in superior planarization of the polished surface. In this process it is important to remove a sufficient amount of material to provide a smooth surface, without removing an excessive amount of underlying materials. Accurate material removal is particularly important in today's submicron technologies where the layers between device and metal levels are constantly getting thinner.
One problem area associated with chemical mechanical polishing is in the area of polishing pads. Typically, the polishing pad or surface is a polyurethane pad. Applicants have determined that variations between polyurethane pads cause variations during the CMP process. For example, two different polyurethane pads used to polishing similar oxide layers on different substrates may result in an oxide thickness variation of 20% to 30%.
The chemical reaction of urea and aminos to form polyurethane is extremely sensitive to contaminants such as water. The contaminants cause variations in the polyurethane pads that bring about variations in the performance of the polyurethane pads. Manufactures of the polyurethane pads have sought to improve the polyurethane pads to eliminate these variations.